Voltage References

FVREF01 IP Traits:

  • Fractional bandgap voltage reference (VREF ≈ VBG/2 ≈ 0.6)
  • Including a bandgap current reference (IREF ≈ VREF/R)
  • Bandgap utilizes parasitic BJT freely available in digital CMOS
  • Design capable of VDD minimum ≈VBE + VDS at cold temperatures
  • Approximate curvature correction via VREF/R feed-back to PTAT-loop
  • VREF output buffer amplifier capable of class AB operations
  • Circuit operates in subthreshold for ultra-low power consumption
  • Manufacturable on trailing-to-bleeding edge CMOS
  • VREF can be calibrated or trimmed to improve TC
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

FVREF02 IP Traits:

  • Fractional bandgap voltage reference (VREF ≈ VBG/2 ≈ 0.6) with low IDD and low VDD by design
  • RPTAT isolated from PTAT loop allows running IPTAT at ultra-low current
  • Operating in subthreshold and running IPTAT at ultra-low currents allows for lower VDD min at cold temperatures
  • Design capable of VDD minimum ≈VREF + VDS
  • Bandgap utilizes parasitic BJT freely available in digital CMOS
  • Manufacturable on trailing-to-bleeding edge CMOS
  • VREF can be calibrated or trimmed to improve TC
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

vREF01 IP Traits:

  • Bandgap voltage reference (VREF ≈ VBG ≈ 1.24) operates in subthreshold with ultra-low IDD
  • Operating in subthreshold and requiring no resistors facilitate small silicon area and operations at ultra-low currents
  • Low noise inherent via summation (instead of multiplication) to generate VPTAT
  • Design capable of VDD minimum ≈VREF + VDS
  • Bandgap utilizes parasitic BJT freely available in digital CMOS
  • Manufacturable on trailing-to-bleeding edge CMOS
  • VREF can be calibrated or trimmed to improve TC
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented