Current References

iREF01 IP Traits:

  • Tiny current reference operating in subthreshold with ultra-low IDD
  • Small size large value active bias resistor (RA) keeps IDD ultra-low
  • Design capable of VDD minimum ≈ VGS + VDS
  • Diverting most leakages (of RA and key FETs) to supplies extends temperature range
  • IREF absolute value chiefly a function of mobility (µ) with inherently narrow variation
  • Narrow variations over process also due to IREF near insensitivity to VTH
  • No passive resistor & no passive capacitor keeps area small & die cost low
  • Manufacturable on trailing-to-bleeding edge CMOS
  • IREF can be calibrated or trimmed to improve TC
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

iREF02 IP Traits:

  • Current reference operating in subthreshold with ultra-low IDD
  • Differential self-cascode (SC) topology generates IREF with low TC
  • Design capable of VDD minimum ≈ VGS + VDS (or 2VGS+VDS)
  • IREF absolute value chiefly a function of mobility (µ) with inherently narrow variation
  • Narrow variations over process also due to IREF near insensitivity to VTH
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Manufacturable on trailing-to-bleeding edge CMOS
  • IREF can be calibrated or trimmed to improve TC
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented