Amplifiers

BUF-AMP01 IP Traits:

  • Buffer-amplifier with near rail-to-rail input-output and (class AB) push-pull output stage
  • Topology of buffer (B) and floating current source (FCS) blocks (that chiefly operate in current-mode) enable wide-bandwidth, low IDD, and low operating VDD
  • Capable of VDD minimum ≈VGS + VDS by design
  • Option to keep IDD low by curbing impact of monitoring the Buffer’s sink-source currents
  • Main amplifier FCTA seamless synthesis with the B and FCS topologies
  • Topology retains inherent FCTA traits: High PSRR and CMRR, and fast slew-rate and settling-time
  • Manufacturable on trailing-to-bleeding edge CMOS
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Buffer amplifier’s input stage can be calibrated or trimmed to improve input offset voltage
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

BUF-AMP02 IP Trait:

  • Small buffer-amplifier with near rail-to-rail input-output and (class AB) push-pull output stage
  • Low-voltage regulated-cascode-current-mirror (RGC) topology utilizing self-cascode (SC) boosts gain synthesized with the main gain amplifier FCTA
  • Capable of VDD minimum ≈2VGS + VDS by design
  • Topology retains inherent FCTA traits: High PSRR, and CMRR and fast slew-rate, and settling-time
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Manufacturable on trailing-to-bleeding edge CMOS
  • Buffer amplifier’s input stage can be calibrated or trimmed to improve input offset voltage
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

BUF-AMP03 IP Trait:

  • Low-noise buffer-amplifier with near rail-to-rail input-output and (class AB) push-pull output stage
  • Patented method enables lowering noise in steady-state by an order of magnitude under apples-to-apples IQ operating currents while boosting slew-rate and settling-time in the face of imbalanced inputs
  • Capable of VDD minimum ≈VGS + 2VDS by design
  • Topology retains inherent FCTA traits: High PSRR and CMRR, and fast slew-rate and settling-time
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Manufacturable on trailing-to-bleeding edge CMOS
  • Buffer amplifier’s input stage can be calibrated or trimmed to improve input offset voltage
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

BUF-AMP04 IP Traits:

  • Small size low-noise buffer-amplifier with near rail-to-rail input-output and (class AB) push-pull output stage
  • Patented method enables lowering noise in steady-state by an order of magnitude under apples-to-apples IQ operating currents (utilizing a winner-take-all technique) while boosting slew-rate and settling-time in the face of imbalanced inputs
  • Capable of VDD minimum ≈2VGS + VDS by design
  • Topology retains inherent FCTA traits: High PSRR and CMRR, and fast slew-rate and settling-time
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Manufacturable on trailing-to-bleeding edge CMOS
  • Buffer amplifier’s input stage can be calibrated or trimmed to improve input offset voltage
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented

BUF-AMP05 IP Traits:

  • High-gain low-noise buffer-amplifier with near rail-to-rail input-output and (class AB) push-pull output stage
  • Topology synthesis a gain boot-strap technique with in a main amplifier FCTA stage to increase gain  
  • Patented method enables lowering noise in steady-state by an order of magnitude under apples-to-apples IQ operating currents while boosting slew-rate and settling-time in the face of imbalanced inputs
  • Capable of VDD minimum ≈3VGS + VDS by design
  • Topology retains inherent FCTA traits: High PSRR and CMRR, and fast slew-rate and settling-time
  • Requiring neither passive capacitors nor resistors, lowers silicon cost and facilitates operations in subthreshold at ultra-low currents
  • Manufacturable on trailing-to-bleeding edge CMOS
  • Buffer amplifier’s input stage can be calibrated or trimmed to improve input offset voltage
  • No clock, no switch-capacitor, and no related noise or injections into substrate
  • Patented