Multiply-Accumulate (MAC) for Neural Networks

SiMAC01 Family IP Traits:

  • Ultra-low-power and tiny SCALAR current-mode multiply-accumulate (iMAC) running MOSFETs in subthreshold
  • Input-output ports receiving a plurality of analog current-inputs (x1 to xN), a scalar analog current-input (y), reference current-input (iR) via Digital word DR, bias current-input (iB) via Digital word DB, generating plurality of analog output-current scaled products (y.x1/iR to y.xN/iR) and or their summation (1/iR).y.∑xi analog current-output
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Inherently better matching between a plurality of analog output-current scaled products
  • Analog input-current source compliance can be arranged with respect to the same power supply VDD or VSS
  • Batch normalization via iDAC’s DR programing iR
  • Topology capable of VDD minimum ≈VGS + VDS
  • Accuracy degrades smoothly with increasing frequency of the current-input signal (without S/H)
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation (iMAC analog current-output (1/iR).y.∑xi
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
      • Generate an offset analog current (iB) via patented RBN method to be subtracted from iMAC current-output (1/iR).y.∑xi
      • Bias analog current (iB) via iDAC’s DB
  • Optional features of IP family:
      • Small size utilizing scalar multiplication patent
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Improve linearity with calibration or trimming
      • Digitally program x1 to xN, y, iR, and iB with iDACs utilizing RBN patent
      • Generate MAC digital-output word via feeding the iMAC output (1/R).y.∑xi-iB to an iADC (utilizing patented iADC patents)
  • patented

QSiMAC01 Family IP Trait:

  • Small-size current-mode multiply-accumulate (iMAC)
  • Inherent multi-quadrant capability
  • Input-output ports receiving plurality of pairs of digital-input (X1-Y1, X1+Y1) to (XN-YN, XN+YN), reference current-input (iR) via Digital word DR, bias current-input (iB) via Digital word DB, and generating plurality of analog output-current products (y1.x1/iR to yN.xN/iR) and or their accumulation (1/iR).∑xi.yi-iB
  • Multiplication options per quarter-square algorithms:
      • Utilizing patented non-linear DAC method
      • Utilizing patented approximate nonlinear digital data conversion method
      • Utilizing patented segmented squaring method
      • Utilizing patented MAC signal quarter-square method
      • Time-multiplexing digital squarers to feed plurality of pairs of iDACs arranged as per RBN patent
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Inherently better matching between plurality of analog output-current products
  • Batch normalization via iDAC’s DR programing iR
  • Topology capable of VDD minimum ≈VGS + VDS
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction (iMAC analog current-output (1/iR).∑xi.yi
      • Bias analog current (iB) via iDAC’s DB
  • Optional features of IP family:
      • Multiple iDAC channels, substantially smaller size, and higher speed utilizing RBN patent
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Capable of asynchronous operations free form clock/injections
      • Improve PSRR cost-effectively utilizing PSR patent
      • Improve linearity with calibration or trimming
      • Generate MAC digital-output word via feeding the iMAC output (1/iR).∑xi.yi-iB to an iADC (utilizing patented iADC patents)
  • patented

MESHiMAC01 Family IP Traits:

  • Compute-in-memory high-speed low-power current-mode multiply-accumulate (iMAC)
  • Input-output ports receiving plurality of pairs of digital-inputs (X1,Y1) to (XN, YN), reference current-input (iR) via Digital word DR, bias current-input (iB) via Digital word DB, and generating plurality of analog output-current products (y1.x1/iR to yN.xN/iR) and or their accumulation (1/iR).∑xi.yi-iB
  • Low-power high-speed multiplication utilizing meshed multiplier system patent (pending) suitable for low-mid resolutions
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Inherently better matching between plurality of analog output-current products
  • Batch normalization via iDAC’s DR programing iR
  • Topology capable of VDD minimum ≈VGS + VDS
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to high-performance bleeding edge digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation current-output (1/iR).∑xi.yi
      • Coupling two opposite polarity signals yields subtraction
      • Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction
      • Bias analog current (iB) via iDAC’s DB
  • Optional features of IP family:
      • Low dynamic IDD utilizing patented side-by-side Memory+Multiplier
      • Multiple iDAC channels, substantially smaller size, and higher speed utilizing RBN patent
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Fast and low power multiplications utilizing meshed multiplier system patent
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Capable of asynchronous operations free form clock/injections
      • Improve PSRR cost-effectively utilizing PSR patent
      • Improve linearity with calibration or trimming
      • Digitize iMAC output (1/iR).∑xi.yi-iB via patented iADC family of IPs
  • patented

BNNiMAC01 Family IP Traits:

  • Tiny Binary-Neural-Network (BNN) Compute-in-memory (CIM) current-mode multiply-accumulate (iMAC)
  • Input-output ports receiving plurality of pairs of digital-inputs (X1,Y1) to (XN, YN), reference current-input (iR) via Digital word DR, bias current-input (iB) via Digital word DB, and generating plurality of analog output-current products (y1.x1/iR to yN.xN/iR) and or their accumulation (1/iR).∑xi.yi-iB
  • Low-power high-speed multiplication utilizing patented iMAC for BNNs
  • Tiny topology in part because of patented current-mode population counting (iPOP) combined with current-mode XOR/XNOR (iXOR/iXNOR)
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Inherently better matching between plurality of analog output-current products
  • Batch normalization via iDAC’s DR programing iR
  • Topology capable of VDD minimum ≈VGS + VDS
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to high-performance bleeding edge digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields population count current-output (1/iR).∑xi.yi
      • Coupling two opposite polarity signals yields subtraction
      • Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Low dynamic IDD utilizing patented side-by-side Memory+iXNOR
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Multi-quadrant operation via bias analog current (iB) via iDAC’s DB
      • Capable of asynchronous operations free form clock/injections
      • Improve PSRR cost-effectively utilizing PSR patent
      • Improve linearity with calibration or trimming
      • Digitize iMAC output (1/iR).∑xi.yi-iB via patented iADC family of IPs
  • patented
  • HYBRID ACCUMULATION METHOD IN MULTIPLY-ACCUMULATE FOR MACHINE LEARNING
  • Patent Pending
  • CURRENT-MODE MIXED-SIGNAL SRAM BASED COMPUTE-IN-MEMORY FOR LOW POWER MACHINE LEARNING
  • Patent Pending