## Multiply-Accumulate (MAC) for Neural Networks

**_{S}iMAC01 Family** IP Traits:

- Ultra-low-power and tiny SCALAR current-mode multiply-accumulate (iMAC) running MOSFETs in subthreshold
- Input-output ports receiving a plurality of analog current-inputs (x
_{1 }to x_{N}), a scalar analog current-input (y), reference current-input (i_{R}) via Digital word D_{R}, bias current-input (i_{B}) via Digital word D_{B}, generating plurality of analog output-current scaled products (y.x_{1}/i_{R}to y.x_{N}/i_{R}) and or their summation (1/i_{R}).y.∑x_{i }analog current-output - ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Inherently better matching between a plurality of analog output-current scaled products
- Analog input-current source compliance can be arranged with respect to the same power supply V
_{DD}or V_{SS} - Batch normalization via iDAC’s D
_{R}programing i_{R} - Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Accuracy degrades smoothly with increasing frequency of the current-input signal (without S/H)
- Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling plurality of same polarity signals yields summation (iMAC analog current-output (1/i
_{R}).y.∑x_{i} - Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction
- Generate an offset analog current (i
_{B}) via patented RBN method to be subtracted from iMAC current-output (1/i_{R}).y.∑x_{i} - Bias analog current (i
_{B}) via iDAC’s D_{B}

- Optional features of IP family:
- Small size utilizing scalar multiplication patent
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming
- Digitally program x
_{1}to x_{N}, y, i_{R}, and i_{B}with iDACs utilizing RBN patent - Generate MAC digital-output word via feeding the iMAC output (1/R).y.∑x
_{i}-i_{B}to an iADC (utilizing patented iADC patents)

- patented

**_{QS}iMAC01 Family **IP Trait:

- Small-size current-mode multiply-accumulate (iMAC)
- Inherent multi-quadrant capability
- Input-output ports receiving plurality of pairs of digital-input (X
_{1}-Y_{1}, X_{1}+Y_{1}) to (X_{N}-Y_{N, }X_{N}+Y_{N}), reference current-input (i_{R}) via Digital word D_{R}, bias current-input (i_{B}) via Digital word D_{B}, and generating plurality of analog output-current products (y_{1}.x_{1}/i_{R}to y_{N}.x_{N}/i_{R}) and or their accumulation (1/i_{R}).∑x_{i}.y_{i}-i_{B} - Multiplication options per quarter-square algorithms:
- Utilizing patented non-linear DAC method
- Utilizing patented approximate nonlinear digital data conversion method
- Utilizing patented segmented squaring method
- Utilizing patented MAC signal quarter-square method
- Time-multiplexing digital squarers to feed plurality of pairs of iDACs arranged as per RBN patent

- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Inherently better matching between plurality of analog output-current products
- Batch normalization via iDAC’s D
_{R}programing i_{R} - Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling plurality of same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction (iMAC analog current-output (1/i
_{R}).∑x_{i}.y_{i} - Bias analog current (i
_{B}) via iDAC’s D_{B}

- Optional features of IP family:
- Multiple iDAC channels, substantially smaller size, and higher speed utilizing RBN patent
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming
- Generate MAC digital-output word via feeding the iMAC output (1/i
_{R}).∑x_{i}.y_{i}-i_{B}to an iADC (utilizing patented iADC patents)

- patented

**_{MESH}iMAC01 Family** IP Traits:

- Compute-in-memory high-speed low-power current-mode multiply-accumulate (iMAC)
- Input-output ports receiving plurality of pairs of digital-inputs (X
_{1},Y_{1}) to (X_{N, }Y_{N}), reference current-input (i_{R}) via Digital word D_{R}, bias current-input (i_{B}) via Digital word D_{B}, and generating plurality of analog output-current products (y_{1}.x_{1}/i_{R}to y_{N}.x_{N}/i_{R}) and or their accumulation (1/i_{R}).∑x_{i}.y_{i}-i_{B} - Low-power high-speed multiplication utilizing meshed multiplier system patent (pending) suitable for low-mid resolutions
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Inherently better matching between plurality of analog output-current products
- Batch normalization via iDAC’s D
_{R}programing i_{R} - Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to high-performance bleeding edge digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling plurality of same polarity signals yields summation current-output (1/i
_{R}).∑x_{i}.y_{i} - Coupling two opposite polarity signals yields subtraction
- Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction
- Bias analog current (i
_{B}) via iDAC’s D_{B}

- Optional features of IP family:
- Low dynamic I
_{DD}utilizing patented side-by-side Memory+Multiplier - Multiple iDAC channels, substantially smaller size, and higher speed utilizing RBN patent
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Fast and low power multiplications utilizing meshed multiplier system patent
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming
- Digitize iMAC output (1/i
_{R}).∑x_{i}.y_{i}-i_{B}via patented iADC family of IPs

- Low dynamic I

- patented

**_{BNN}iMAC01 Family** IP Traits:

- Tiny Binary-Neural-Network (BNN) Compute-in-memory (CIM) current-mode multiply-accumulate (iMAC)
- Input-output ports receiving plurality of pairs of digital-inputs (X
_{1},Y_{1}) to (X_{N, }Y_{N}), reference current-input (i_{R}) via Digital word D_{R}, bias current-input (i_{B}) via Digital word D_{B}, and generating plurality of analog output-current products (y_{1}.x_{1}/i_{R}to y_{N}.x_{N}/i_{R}) and or their accumulation (1/i_{R}).∑x_{i}.y_{i}-i_{B} - Low-power high-speed multiplication utilizing patented iMAC for BNNs
- Tiny topology in part because of patented current-mode population counting (iPOP) combined with current-mode XOR/XNOR (iXOR/iXNOR)
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Inherently better matching between plurality of analog output-current products
- Batch normalization via iDAC’s D
_{R}programing i_{R} - Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to high-performance bleeding edge digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling plurality of same polarity signals yields population count current-output (1/i
_{R}).∑x_{i}.y_{i} - Coupling two opposite polarity signals yields subtraction
- Inputting plurality of pairs of same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Low dynamic I
_{DD}utilizing patented side-by-side Memory+iXNOR - Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Multi-quadrant operation via bias analog current (i
_{B}) via iDAC’s D_{B} - Capable of asynchronous operations free form clock/injections
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming
- Digitize iMAC output (1/i
_{R}).∑x_{i}.y_{i}-i_{B}via patented iADC family of IPs

- Low dynamic I

- patented

- HYBRID ACCUMULATION METHOD IN MULTIPLY-ACCUMULATE FOR MACHINE LEARNING
- Patent Pending

- CURRENT-MODE MIXED-SIGNAL SRAM BASED COMPUTE-IN-MEMORY FOR LOW POWER MACHINE LEARNING
- Patent Pending