## Multipliers

** iMULT01 Family** IP Traits:

- Two current-input (x & y), one reference current-input (R), to one current-output (z=x.y/R) multiplier (iMULT) arranged in accordance with a patented Difference Amplification Multiplication method
- MOSFETs operate in subthreshold to facilitate ultra-low power consumption
- ± 1% to ± 2% typical accuracy achievable (depending on W/L and process node)
- iMULT utilizes parasitic BJT (available in standard digital CMOS for free) to receive its current-input signals
- Wide current-input range is facilitated by BJTs (with inherently larger current drive) that carry the current-input signal, not bounded by MOSFET’s subthreshold operating current limit
- Topology capable of V
_{DD}minimum ≈V_{BE}+ V_{DS} - Because summation in current mode is simply the coupling of plurality of signals, the patent topology facilitates scalar multiplication (e.g., z=y.Σx/R), wherein one BJT can receive plurality of current-input signals (e.g., x
_{1}to x_{N}) whose summation (Σx) is multiplied (scaled) by another BJT’s current-input signal (e.g., ‘y’) - Accuracy degrades smoothly (as opposed to abruptly) with increasing frequency of the current-input signal (without an input S/H)
- Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

** iMULT02 Family **IP Traits:

- Small-size two current-input (x & y), one reference current-input (R), to one current-output (Z=x.y/R) multiplier (iMULT) arranged in accordance with a patent (pending) Winner-Take-All Multiplication method
- Current-input signal’s compliance can be arranged with respect to V
_{DD}, V_{SS}, or complementary (e.g., ‘x’ with respect to V_{DD}and ‘y’ with respect to V_{SS}) - ± 1% to ± 2% typical accuracy achievable (depending on W/L and process node)
- MOSFETs operate in subthreshold to facilitate ultra-low power consumption
- Full scale current-input programmed by reference current-input R and its range is restricted to keep FETs operating in subthreshold
- Topology capable of V
_{DD}minimum ≈2V_{GS}+ V_{DS} - Accuracy degrades smoothly (as opposed to abruptly) with increasing frequency of the current-input signal (without an input S/H)
- Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

** iMULT03 Family** IP Traits:

- Very small-size multiplier (iMULT) with two analog current-input (x & y), one reference current-input (R), generating one analog current-output (z=x.y/R)
- Multiplier utilizes current-input current-output Multiplication patent (pending) method and operates in subthreshold for ultra-low I
_{DD} - Tiny iMULT optimized for applications requiring substantial number of multipliers (e.g., 100s of iMULTs)
- ± 1% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Full scale current-input programmed by reference current-input R and its range is restricted to keep FETs operating in subthreshold
- Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Accuracy degrades smoothly (as opposed to abruptly) with increasing frequency of the current-input signal (without an input S/H)
- Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

**_{NL}iMULT01 Family** IP Traits:

- Ultra-low power multiplier utilizing a patented Non-Linear Multiplication Method (e.g., logarithmic, quarter-square) which can be arranged as:
- Receiving pair of digital-inputs (X,Y) and a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- Receiving pair of analog current-inputs (x, y) and a reference analog input-current (R), and generating a digital-output (Z = X.Y/R)

- Multiplier’s topology utilizes data-converters whose reference-network are programmed in accordance with their respective non-linear profiles
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Programmable reference network for linear or non-linear transfer function
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

**_{SM}iMULT01 Family** IP Traits:

- Multiplier with digital-inputs (X, Y), a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- Ultra-low power utilizing a Segmented Mixed-Mode multiplication method
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Topology has inherent computational efficiency because:
- Digital input word’s MSP & LSP multiplied and cross-multiplied via smaller current-mode multiplying D/A converters whose outputs are scaled & summed
- Scaling via current mirrors, and summation via coupling of wires

- Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Programmable reference network for linear or non-linear transfer function
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Multi-staging Data Converters for different cost-performance objectives
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

**_{ SM}iMULT02 Family** IP Traits:

- Multiplier with analog-inputs (x, y), a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- Ultra-low power utilizing a patented Segmented Mixed-Mode Divide-and-Conquer multiplication method
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Topology capable of V
_{DD}minimum ≈V_{GS}+ V_{DS} - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Program reference network for linear or non-linear transfer function
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Multi-staging Data Converters for different cost-performance objectives
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

**_{iDAC}iMULT01 Family** IP Traits:

- Utilizing a patented Floating iDAC method, Multiplier with digital-inputs (X, Y), a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Area savings in lieu of avoiding current-mirrors (required to arrange conventional multipliers using iDAC)
- Capable of V
_{DD}minimum ≈V_{GS}+ 2V_{DS }by design - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Programmable reference network for linear or non-linear transfer function
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Multi-staging Data Converters for different cost-performance objectives
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

** _{QS}iMULT01** Family IP Traits:

- Current mode multiplier (iMULT) utilizing a patented Quarter-Square method via non-linear data-converters
- Multiplier with digital-inputs (X+Y, X-Y), a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Inherent multi-quadrant operation
- Capable of V
_{DD}minimum ≈V_{GS}+ 1V_{DS }by design - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Programmable reference network for linear or non-linear transfer function
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Multi-staging Data Converters for different cost-performance objectives
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

** _{MESH}iMULT Family** IP Traits:

- High-speed current mode multiplier (iMULT) utilizing a patented Meshed Multiplier method
- Multiplier with digital-inputs (Y, X), a reference analog input-current (R), and generating an analog current-output (z = x.y/R)
- ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
- Suitable for high-speed & low-mid resolution applications
- High-speed is achievable in part because, unlike conventional multipliers arranged with multiplying iDACs. the patented meshed topology avoids current-mirrors
- Capable of V
_{DD}minimum ≈V_{GS}+ V_{DS }by design - Less costly because circuit is free from passive resistors and passive capacitors
- Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
- General benefits for operating in current-mode:
- Faster dynamic response due to inherent small voltage-swings in current mode signal processing
- Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
- Coupling two same polarity signals yields summation
- Coupling two opposite polarity signals yields subtraction
- Inputting two same polarity signals across a current mirror yields subtraction

- Optional features of IP family:
- Programmable to increase speed with more I
_{DD} - Programmable for ultra-low power consumption with lower speeds
- Programmable reference network for linear or non-linear transfer function
- Synthesize Floating DAC patent to reduce size
- Capable of asynchronous operations free form clock/injections
- Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
- Improve PSRR cost-effectively utilizing PSR patent
- Multiple channels, smaller size, and higher speed utilizing RBN patent
- Multi-staging Data Converters for different cost-performance objectives
- Improve linearity with calibration or trimming

- Programmable to increase speed with more I

- patented

- DIGITAL APPROXIMATE MULTIPLIERS FOR MACHINE LEARNING AND ARTIFICIAL INTELLIGENCE APPLICATIONS
- Patent Pending

- DIGITAL APPROXIMATE SQUARER FOR MACHINE LEARNING
- Patent Pending