A/D Converters

TFiADC01 Family IP Traits:

  • Pseudo-FLASH current-input low-power Analog-to-Digital Converter (TFiADC)
  • Patented Reference Network architecturally monotonic
  • ± 0.5% to ± 2% typical accuracy may be achievable (depending on W/L and process node)
  • Concurrent analog & digital computation helps smooth accuracy degradation with rising input frequency
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Improve linearity with calibration or trimming
  • patented

TiADC01 Family IP Traits:

  • Small-size multi-stage current-input low-power Analog-to-Digital Converter (TiADC)
  • Patented Most-Significant-Portion (MSP) of iADC’s first stage reference network inherently enhances the accuracy of the overall iADC
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Concurrent analog & digital computation helps smooth accuracy degradation with rising input frequency
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging ADC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • patented

GiADC01 Family IP Traits:

  • Low-glitch small-size current-input low-power gray-code Analog-to-Digital Converter (GiADC)
  • Patented gray-code signaling improves accuracy, speed, reduces IDD, shrinks size, and lowers cost
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Concurrent analog & digital computation helps smooth accuracy degradation with rising input frequency
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging ADC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • patented

TREEiADC01 Family IP Traits:

  • Near-Zero-glitch current-input low-power Tree reference-network Analog-to-Digital Converter (TREEiADC)
  • Patented topology’s independent analog & digital computation which makes iADC glitch-free
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Concurrent analog & digital computation helps smooth accuracy degradation with rising input frequency
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging ADC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • Patented

TREEriADC01 Family IP Traits:

  • Tiny low-power current-input ripple-tree reference-network Analog-to-Digital Converter (TREEriADC)
  • Rippling residual analog-current-input to digital-outputs reduces IDD and substantially reduces die size/cost
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling plurality of same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging ADC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • patented