Ai Linear, as a startup, has thus far successfully demonstrated proof of silicon for its ultra-low-power building blocks needed for “AI Inference for Sensors“.  These building blocks are analog and mixed-mode intellectual property (IP) in five test chips fabricated at TSMC using 65nm and 180nm standard digital CMOS processes. These test chips incorporate several of Ai Linear’s patented circuits, which serve as essential building blocks, including IBIAS, IREF, VREF, ADCs (in both voltage and current modes), and MAC neural network components. The silicon layout images below represent significant milestones in validating Ai Linear’s proprietary technologies.