D/A Converters

iDAC01 Family IP Traits:

  • Small-size digital-input to analog current-output Digital-to-Analog Converter (iDAC) utilizing the Factorized iDAC method.
  • Smaller size by roughly 3X compared to conventional iDACs, which can reduce glitch and lower cost
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Capable of VDD minimum ≈VGS + VDS by design
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling two same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Program reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging DAC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • patented

iDAC02 Family IP Traits:

  • Compact multi-channel digital-input to analog current-output Digital-to-Analog Converter (iDAC) utilizing the Reference Bias Network iDAC method.
  • For double digit channels of iDACs, the patented topology size can smaller by more than an order of magnitude compared to conventional multi-channel iDACs
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Substantially higher speed and lower glitch compared to conventional multi-channel iDACs
  • Substantially lower output capacitance (at the analog current-output port) improves the capacitive loading onto subsequent stages (e.g., current mode ADC) which improves system’s dynamic response
  • Inherent matching between iDAC channels
  • Capable of VDD minimum ≈VGS + 2VDS by design 
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling two same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multi-staging DAC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • patented

NiDAC01 Family IP traits:

  • Non-linear digital-input to analog current-output Digital-to-Analog Converter (iDAC) utilizing the Non-linear iDAC method
  • Non-linear iDAC topology suitable for performing quarter-square multiplication (facilitates inherent multi-quadrant multiplication)
  • ± 0.5% to ± 2% typical accuracy achievable (depending on W/L and process node)
  • Capable of VDD minimum ≈VGS + 2VDS by design
  • Less costly because circuit is free from passive resistors and passive capacitors
  • Manufacturable on low-cost trailing-edge to bleeding edge high-performance digital CMOS
  • General benefits for operating in current-mode:
      • Faster dynamic response due to inherent small voltage-swings in current mode signal processing
      • Current peak-to-peak swings at analog I/O ports are less restricted (compared to voltage mode)
      • Coupling two same polarity signals yields summation
      • Coupling two opposite polarity signals yields subtraction
      • Inputting two same polarity signals across a current mirror yields subtraction
  • Optional features of IP family:
      • Programmable to increase speed with more IDD
      • Programmable for ultra-low power consumption with lower speeds
      • Programmable reference network for linear or non-linear transfer function
      • Capable of asynchronous operations free form clock/injections
      • Single-quadrant or multi-quadrant operation utilizing multi-quadrant patent
      • Improve PSRR cost-effectively utilizing PSR patent
      • Multiple channels, smaller size, and higher speed utilizing RBN patent
      • Multi-staging DAC for different cost-performance objectives
      • Improve linearity with calibration or trimming
  • Patented